1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to semiconductor fabrication processes employing double gate or “fin” FET transistors.
2. Description of Related Art
A conventional metal-oxide-semiconductor (MOS) transistor has a structure in which a gate electrode is displaced above the transistor channel region by an intermediate gate dielectric film. The region below the channel may include the bulk substrate or an epitaxial film. The transistor is operated by applying a bias to the gate electrode. The bulk material is likely grounded or biased to a constant voltage. Thus, the conventional transistor may be described as having a single-sided gate since the gate exists on only one side of (i.e., above) the channel.
It is generally recognized that single-sided gate transistors inherently exhibit operational characteristics, including leakage current, drive current, and sub-threshold slope, that are less than ideal. These parameters are particularly critical in low power applications such as wireless technology. Multiple-gate transistor structures, in which gate dielectrics and gate electrodes are formed on two (or more) sides of the transistor channel, have been proposed to address this problem.
One example of a multiple gate transistor is the “fin” FET, so named because the transistor channel is a fin or wall of silicon positioned above the underlying substrate. A gate dielectric is formed on the faces of the fin and a gate electrode is formed by depositing and patterning polysilicon or another suitable material. The exposed portions of the fin (i.e., the portions not covered by the gate electrode) serve as the source/drain regions in the finished transistor structure.
Reducing resistivity in the source/drain regions is important in the design of high performance transistors including multiple gate transistors. This goal is typically achieved, at least in part, by using a silicide process in which a material that is reactive with silicon, such as titanium, is deposited over a transistor and heated in an oven. During this heat step, a silicide is formed wherever the deposited material contacts exposed silicon. The exposed silicon includes the exposed source/drain regions and an upper surface of the silicon-based gate electrode. Additional reduction of resistivity in the source/drain regions may be achieved, at least in part, by growing silicon or silicon germanium selectively on the exposed silicon faces. To prevent an electrical short between the gate and the source/drain regions from forming during the silicide process, a dielectric spacer is formed adjacent the gate sidewalls prior to silicide deposition. The silicide material does not react with the underlying dielectric. The unreacted silicide material is then removed following the silicide heat treatment.
In a fin-based process, conventional processing as described above has an undesirable consequence. Specifically, the dielectric spacer formed following gate etch forms, not only on the gate electrode sidewalls, but also the vertically oriented primary fin faces in the source/drain regions (i.e., the regions of the fin not covered by the gate electrode). Thus, after spacer formation, the only part of the source/drain regions that is exposed and capable of being silicided is along the very small, top surface of the fins. It would be desirable to implement a process employing a selective epitaxial process or silicide process or both in which the primary fin faces are exposed for silicide and/or selective epitaxial processing while still preventing gate-to-source/drain short circuits.